| AutoBench 1.1 | | STMicro STM32F2xx - 120MHz | 4.0.0.524 | 46.2 | | OTB | 04/14/10 | |
| | | STMicro STR91xFA - 96MHz | IAR 4.41A | 20.0 | | OTB | 06/01/07 | There are no L1 I or D caches on the device. The core has a Tightly Coupled Memory interface for the I and D. On the ITCM there is burst Flash with memory acceleration, on DTCM there is standard 1-cycle SRAM. |
| | | STMicro ST20C2 50 | STMicro ST20 ANSI C Compiler v1.8 | 3.6 | | OTB | 03/28/00 | |
| | | ST20C2 50 | ST20 ANSI C Compiler v1.8 | 1.0 | | OTB | 03/22/00 | |
| CoreMark 1.0 | | STMicroelectronics STM32 90nm | KEIL 4.0.0.524 | 1.905 | | OTB | 04/20/10 | |
| | | ST20C2 50 | ST20 ANSI C Compiler v1.8 | N/A | | OTB | 03/29/00 | |
| | | ST20C2 50 | ST20 ANSI C Compiler v1.8 | 11.4 | | OTB | 03/22/00 | |
| | | ST20C2 50 | ST20 ANSI C Compiler v1.8 | N/A | | OTB | 03/22/00 | |
